Method and apparatus for analyzing post-layout timing violations

ABSTRACT

A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report of consolidated timing violations. The report of consolidated timing violations can then be analyzed by a verification engineer.

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuit designverification, and more particularly to a system, method, and apparatusfor analyzing post layout timing violations.

Simulation programs are frequently used for testing integrated circuits.Integrated circuit production is characterized by high initial costs forthe production of the first “copy” followed by low marginal costs foreach successive copy. Testing of a design for an integrated circuitprior to production is almost imperative.

The design timing verification starts with the delivery of a designlayout of the integrated circuit. A design layout is a functional andtiming representation of the design of an integrated circuit. The designlayout starts from an implementation description of the functionalitythat is synthesized from a behavioral language description. Duringdesign verification, a design layout is tested for operational errors.The operational errors are then used to diagnose any errors in thedesign layout and modify the design layout. The modified design layoutis then retested. The testing and debugging cycle continue until adesign layout is developed which meets the design verificationrequirements. The final design layout is then used for production ofintegrated circuits.

The design layouts are tested by simulating the operation of the designlayouts. The operation of the design layouts is simulated by what areknown as simulation tools. One of the most popular simulation tools isknown as the Verilog™ simulator. The Verilog™ simulator performs avariety of simulations which test various aspects of the integratedcircuit, including timing simulations.

Timing simulations are used to test the synchronization of the designlayout. One area of testing tests the arrival of signals at flip-flops.In an integrated circuit, latches are characterized by a clocked inputwhich is controlled by a clock. The clock generates a clock signal witha brief pulse at predetermined time intervals. The input signals mustarrive prior to the clock signal. If the signal arrives after the clocksignal, the latch will not recognize the input. To avoid the foregoingproblem, a design layout is simulated. When an input signal does notarrive at the expected time during the simulation, a timing violationoccurs. The foregoing simulation is known as a post-layout gate levelback annotated simulation.

The timing violations during a post-layout gate level back annotatedsimulation are reported in a log file. The log file includes recordswhich indicate various information related to each timing violation,such as the time, location, and type of timing violation. The log filecan then be analyzed by a verification engineer to modify the designlayout.

Analysis of the log file is very time consuming. There are usually anextremely high number of timing violations reported in the log file.Many of the high number of timing violations are either not useful fordiagnostic purposes or redundantly indicate a problem. Additionally, thetiming violations are not sorted in a manner that is useful fordebugging. As a result, analysis of the timing violations is done on abrute force violation-by-violation basis. Due to the lack oforganization of the timing violations, overall trends are hard toidentify from individual timing violations, because the individualtiming violations are sparsely located throughout the log file.

Accordingly, it would be advantageous if a tool for analyzing timingviolations is provided. Further limitations and disadvantages ofconventional and traditional approaches will become apparent to one ofskill in the art, through comparison of such systems with embodimentspresented in the remainder of the present application with references tothe drawings.

BRIEF SUMMARY OF THE INVENTION

Presented herein is a method, and apparatus for analyzing timingviolations which are generated during post-layout gate level backannotated simulations. The log file generated by a post-layout gatelevel back annotated simulator is parsed by a script. The script uses acombination of filtering, consolidating, and sorting to generate areport of consolidated timing violations. The report of consolidatedtiming violations presents information about the timing violations whichis more concise, better organized, and from which it is easier toidentify trends.

Numerous timing violations occur shortly after a simulated power on orsystem reset. These particular timing violations are usually notindicative of design errors in the design layout. Nevertheless, thesetiming violations are among the many that are reported in the log fileby the simulator. The script filters the log file and disregards anytiming violations which are found to occur within a predetermined timeinterval after a simulated power-on or system reset. This reduces thenumber of timing violations which must be sifted through duringdebugging.

Many timing violations indicate redundant information. For example, abus violating a timing width specification results in most, if not all,of the bits of the bus to have a timing violation. A timing violation isrecorded in the log file for each of the bits. In the case of a 32-bitbus, it is possible for 32 timing violations to be reported. The scriptsearches for and consolidates the information regarding substantiallycontemporaneous timing violations occurring with respect to the samemodule of the circuit. In the report of consolidated timing violations,the consolidated information is presented in one entry.

Presentation of consolidated information regarding substantiallycontemporaneous timing violations at the same module results in a reportwhich is organized on a module-by-module basis. Organization on amodule-by-module basis makes trend identification easier because timingviolations which are sparsely located throughout the log file arerepresented together in a single entry.

These and other advantages and novel features of the embodiments in thepresent application will be more fully understood from the followingdescription and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a flow diagram describing an exemplary design verificationprocess wherein the present invention can be practiced;

FIG. 2 is a block diagram of an exemplary log file containing timingviolation reports;

FIG. 3 is a global array in accordance with an embodiment of the presentinvention;

FIG. 4 is a flow diagram describing timing violation reportconsolidation in accordance with an embodiment of the present invention;

FIG. 5 is an exemplary timing violation report in accordance with thepresent invention; and

FIG. 6 is a block diagram of an exemplary hardware environment whereinthe present invention can be practiced.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is illustrated a flow diagram describingan exemplary design verification process wherein the present inventioncan be practiced. The process begins with the delivery (105) of a designlayout. A design layout is a representation of the design of anintegrated circuit, as well as the layout of the design on a substrate.

After the design layout is developed, a simulation tool is used tocalculate (110) the timing data for the design layout. The calculatedtiming data is stored in a timing data file in a predetermined format,such as the IEEE Standard Delay Format (SDF) P1497, which isincorporated by reference herein. The calculated timing data includescalculated propagation delays between various elements in the designlayout. The calculated propagation delays are based on various factorsincluding the physical distance that a signal must travel on theintegrated circuit. Since the calculated timing data is not based onempirical data, a degree of deviation may exist between the calculatedtiming data and the actual propagation delay, when the integratedcircuit is actually made. Therefore a safety margin (115) may be addedto the timing data file prior to simulating the design layout.

A post-layout gate level back annotated simulation (120) is thenconducted for the design layout using the data in the timing data fileby a simulator. The post-layout gate level back annotated simulationgenerates a log file of all timing violations which occurred during thesimulation. For example, a setup timing violation occurs when anexpected signal has not arrived at its destination at the time requiredA hold timing violation occurs when a signal is not held stable for asufficient amount of time after the data is examined. A width violationis a violation of the width requirement for a pulse, which is usuallyindicative of a glitch.

Referring now to FIG. 2, there is illustrated an exemplary log 205containing timing violation reports 210. Each timing violation report210 reports various information about a particular timing violation. Thetiming violation report 210 includes the warning type 215 a, time of theclock event 215 b, time of the data event 215 c, setup time limit 215 d,hold time limit 215 e, and scope 215 f.

In this example, the timing violation reported by timing violationreport 210 a occurred at bit 18 of accum_reg at time, T, T=1617750 pS,the timing violation reported by timing violation report 210 b occurredat bit 9 of accum_reg at T=1617750 pS, the timing violation reported bytiming violation report 210 c occurred at bit 1 of debug_data_reg atT=1617760 pS, and the timing violation reported by timing violationreport 210 d occurred at bit 3 of accum_reg at T=1617760 pS.

Analysis of the log file 205 is time consuming. A typical log file caninclude thousands of timing violation reports 210. Many of the timingviolations are associated with the same design element. For example,timing violation report 210 a and 210 b are associated with timingviolations which happened at bits 18 and 9, respectively, of accum_regat the same time. A bus committing a timing violation is frequentlycharacterized by timing violations for most, if not all, of theconstituent lines of the bus. If a 32-bit bus commits a timingviolation, potentially 32 timing violation reports 210 are generated.Additionally, a great number of timing violations normally occurimmediately after a simulated power-on or system reset. Although theseviolations are not indicative of any error in the design layout, thetiming violations are among the many timing violations which arereported in the log file.

Referring again to FIG. 1, at 125, the log file is parsed by a script,thereby generating a report of consolidated timing violations. Thereport of consolidated timing violations presents the informationregarding the timing violations in a more concise and organized mannerto facilitate diagnostics and debugging (130) of the design layout.

The script uses a global array to filter, consolidate, and sort thetiming violations of the log file 200. The contents of the global arrayare then presented in a report of consolidated timing violations.Referring now to FIG. 3, there is illustrated a block diagram of anexemplary global array 305. The global array 305 includes a plurality ofrecords 310. Each record 310 includes fields for warning type 315 a,time of clock event 315 b, time of data event 315 c, setup time limit315 d, hold time limit 315 e, scope 315 f, amount of violation 310 g,number of warnings 315 h, time of last warning 315 i, name of theviolating pin on violating flip-flop 315 j, bit positions on a busreporting timing violations 315 k, and time of first warning 3151. Thefields 315 a-315 f relate directly to the warning type 215 a, time ofclock event 215 b, time of data event 215 c, setup time limit 215 d,hold time limit 215 e, and scope 215 f. As the script parses the logfile 205, the script records information 215 a-215 f about the timingviolations 210, in the fields 315 a-315 f of the global array.

The remaining fields, 315 g-3151, are metrics calculated by the script.The violation time 315 g is the difference between the budgeted time andthe actual time, and is calculated from the limits (setup or hold) andthe difference in time between the clock and data events. The number ofwarnings 315 h, time of the last warning 315 i, bit position 315 k, andtime of first warning 3151 are used by the script to report consolidatedinformation regarding multiple timing violations that occur at aparticular module, for example, a bus.

As noted above, a large number of substantially contemporaneous timingviolations 210 in a particular module can be the result of a singlecause. Reporting consolidated information about substantiallycontemporaneous timing violations 210 in a particular module,advantageously reduces the number of records which the verificationengineer must analyze, and presents a trend of timing violations whichis useful for diagnostic purposes.

Referring now to FIG. 4, there is illustrated a flow diagram describingthe operation of the script. At 405, the script sets up a data structurefor the global array. At 410, the script opens the log file 205generated by the post layout simulation and begins parsing theviolations. At 415, the script examines the next timing violation in thelog file 205. As noted above, numerous timing violations 210 arereported immediately after system reset which are not indicative ofdesign layout errors. These timing violations 210 are filtered bydetermining if the timing violation occurred within the predeterminedtime from system startup (420). In the case where the timing violationoccurred within the predetermined time from system startup, the timingviolation 210 is disregarded (425) and not recorded in the global array305.

If the timing violation 210 is not within the predetermined timeinterval from a system reset during 420, the script examines the timingviolation 210 to determine whether the timing violation occurred at abus (430). In the case where the timing violation occurred at a busduring 425, the bit position is separated (435) from the scope 215 f.The scope for a bus bit usually is denoted by a suffix which includes anunderscore followed by a number indicating the bit position. Removal ofthe suffix for bus bits from the scope of a bus bit insures that all ofthe different bits on the bus will have the same scope. In the casewhere the timing violation did not occur at a bus, 435 is bypassed.

At 440, the scope of the timing violation 210 is searched among all ofthe previous entries in the scope field 315 f in the previous records310 stored in the global array 305 to correlate the present timingviolation with information about other timing violations occurring atthe same scope. If at 445, another record 310 is found with the samescope field 315 f as the present timing violation 210, the record 310 isupdated (450).

The record 310 is updated (450) by incrementing the number of warningsfield 315 h, and storing the time of the data event 215 c in the time oflast warning field 315 i. Additionally, if the timing violation 210pertains to a bus, the bit position which was separated from the scopeis appended to the bit positions field 315 k.

If at 445, another record 310 is not found with the same scope field 315f as the present timing violation 210, a record 310 is added (455) tothe global array. The information 215 a-215 f is recorded at fields 315a-315 f. The timing violation field 315 g is calculated from the setuptimes 315 d, the hold times 315 e and the difference in time between theclock 315 b and data events 315 c. The number of warnings is set to 1.The time of the first warning and the time of the last warning are bothset to the time of data event 215 c.

After 450 or 455, a determination is made at 460 whether the timingviolation 210 is the last timing violation in the log file 405. In thecase where the timing violation 210 is not the last timing violation inthe log file 405 during 460, 415-460 are repeated for the next timingviolation 210 in the log file 205. In the case where the present timingviolation 210 is the last timing violation in the log file 205, a reportof consolidated timing violations is prepared at 465 for use by theverification engineer.

Referring now to FIG. 5, there is illustrated an exemplary report ofconsolidated timing violations 505. The report includes the violationtype 315 a, the number of warnings 315 i, the scope 315 f, the bitpositions 315 k, if pertaining to a bus, the time of the first violation3151 and the time of the last violation 315 i. In the case of a bus, thescope 315 f that is reported is the original scope separated from thesuffix.

In the illustrated example, the first entry 510 a in the report ofconsolidated timing violations 505, reports that 19 timing violationsoccurred at the bus “accum_reg”, at bit positions 0-18, betweenT=1617740 pS, and 1617750 ps. The entry 510 b reports that 7 timingviolations occurred at the bus “data_reg”, at bit positions 0-7, betweenT=1617750 pS to 1617760 pS.

As can be seen, analysis of the report of consolidated timing violations505 is less time consuming than the log file 205. First, timingviolations 210 which occurring within a predetermined amount of timeafter a simulated power-on or reset are filtered from the report ofconsolidated timing violations 505. Secondly, the timing violations 210are reported on a consolidated basis for common modules, such as a bus.This significantly reduces the number of records 310 which must beanalyzed. Thirdly, because the timing violations 210 are consolidated bymodule, the report of consolidated timing violations 505 presentation ofthe information regarding the timing violations is organized on amodule-by-module basis.

Recordation of the first 315 l and last timing violation 315 i times andthe number of violations 315 i can be also be useful in debugging. Byexamining the first 315 l and last timing violation 315 i times and thenumber of violations 315 i, a design engineer can determine whether thetiming violations were localized in time or cyclical in nature. Forexample, where the timing violations are localized in time, theviolations may be indicative of problems associated with programming aregister. Timing violations which are cyclical in nature are indicativeof problems associated with a clock.

Organization on a module-by-module basis allows for easieridentification of a trend from a individual timing violations 210. Forexample, those skilled in the art will recognize that both the entries510 a and 510 b are indicative of buses violating a width timingspecification due to the high number of bits in errors at substantiallythe same time. Also, because both buses violated the width timingspecification at substantially the same times, it is likely that a clockglitch occurred in the vicinity of the buses.

Referring now to FIG. 6, a representative hardware environment for acomputer system 58 for practicing the present invention is depicted. ACPU 60 is interconnected via system bus 62 to random access memory (RAM)64, read only memory (ROM) 66, an input/output (I/O) adapter 68, a userinterface adapter 72, a communications adapter 84, and a display adapter86. The input/output (I/O) adapter 68 connects peripheral devices suchas hard disc drives 40, floppy disc drives 41 for reading removablefloppy discs 42, and optical disc drives 43 for reading removableoptical disc 44 (such as a compact disc or a digital versatile disc) tothe bus 62. The user interface adapter 72 connects devices such as akeyboard 74, a mouse 76 having a plurality of buttons 67, a speaker 78,a microphone 82, and/or other user interfaces devices such as a touchscreen device (not shown) to the bus 62. The communications adapter 84connects the computer system to a network 92. The display adapter 86connects a monitor 88 to the bus 62.

The communications adapter 84 connects the computer system 58 to othercomputers systems 58 over network 92. The computer network 92 cancomprise, for example, a local area network (LAN), a wide area network(WAN), or the internet. Additionally, a particular one of the computersystems 58 s can act as a server. A computer server 58 a centralizesfiles and functions and provides access to the files and functions tothe other computer systems 58 within the network 92.

An embodiment of the present invention can be implemented as sets ofinstructions resident in the random access memory 64 of one or morecomputer systems 58 configured generally as described in FIG. 6. Untilrequired by the computer system 58, the set of instructions may bestored in another computer readable memory, for example in a hard discdrive 40, or in removable memory such as an optical disc 44 for eventualuse in an optical disc drive 43, or a floppy disc 42 for eventual use ina floppy disc drive 41. Those skilled in the art will recognize that thephysical storage of the sets of instructions physically changes themedium upon which it is stored, electrically, magnetically, chemically,or mechanically, so that the medium carries computer readableinformation.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt particular situation or material tothe teachings of the invention without departing from its scope. Forexample, the flow diagram of FIG. 4 can be implemented as a series ofinstructions residing in a memory for execution by a processor.Therefore, it is intended that the invention not be limited to theparticular embodiment(s) disclosed, but that the invention will includeall embodiments falling within the scope of the appended claims.

1. A method for simulating an integrated circuit, said methodcomprising: consolidating a plurality of records of timing violations,wherein each of said plurality of records reports a timing violation fora same module in a simulated integrated circuit; and generating a reportbased on said consolidating, wherein said report comprises one recordwhich includes information from the plurality of records.
 2. The methodof claim 1, wherein consolidating the portion of the plurality ofrecords further comprises: consolidating the plurality of records oftiming violations, wherein each of said plurality of records reports atiming violation for a same bus.
 3. The method of claim 2, whereinconsolidating the plurality of records, further comprises separating asuffix from a module name for the bus.
 4. The method of claim 3, furthercomprising recording bits of said bus within timing violations.
 5. Themethod of claim 1, further comprising recording a time where a firsttiming violation occurs and recording a time where a last timingviolation occurs for the plurality of records.
 6. The method of claim 1,wherein consolidating a portion of the plurality of records furthercomprises: consolidating the plurality of records of timing violations,wherein each of said plurality of records reports a timing violationduring a predetermined time interval.
 7. The method of claim 1, furthercomprising: filtering timing violations occurring within a predeterminedperiod of time after a simulated power-up or system reset.
 8. An articleof manufacture comprising computer readable medium, wherein the computerreadable medium stores a plurality of executable instructions, andwherein the plurality of executable instructions cause: consolidating aplurality of records of timing violations, wherein each of saidplurality of records reports a timing violation for a same module in asimulated integrated circuit; and generating a report based on saidconsolidating, wherein said report comprises one record which includesinformation from the plurality of records.
 9. The article of manufactureof claim 8, wherein consolidating the plurality of records furthercomprises: consolidating the plurality of records of timing violations,wherein each of said plurality of records reports a timing violation fora same bus.
 10. The article of manufacture of claim 9, whereinconsolidating the plurality of records, further comprises separating asuffix from a module name for the bus.
 11. The article of manufacture ofclaim 10, wherein the plurality of instructions further cause recordingbits of said bus within timing violations.
 12. The article ofmanufacture of claim 8, wherein the plurality of instructions furthercause recording a time where a first timing violation occurs andrecording a time where a last timing violation occurs for the pluralityof records.
 13. The article of manufacture of claim 8, whereinconsolidating the plurality of records further comprises: consolidatingthe plurality of records of timing violations, wherein each of saidplurality of records reports a timing violation during a predeterminedtime interval.
 14. The article of manufacture of claim 8, wherein theplurality of instructions further cause filtering timing violationsoccurring within a predetermined period of time after a system reset.15. A method for analyzing timing violations, said method comprising:examining a scope associated with each of a plurality of timingviolations; comparing the scope associated with each of the plurality oftiming violations to a scope associated with each of a plurality ofrecords in an array; updating one of the records in the array, wherein aparticular scope associated with a particular one of the plurality ofthe timing violations is the same as the scope associated with said oneof the records in the array; and adding a record to the array for aparticular timing violation, wherein the particular scope associatedwith the timing violation does not match any of the scopes associatedwith any of the records in the array.
 16. The method of claim 15,further comprising: determining whether the particular one of theplurality of timing violations is associated with a bus; and removing asuffix from the scope, wherein the particular one of the timingviolations is associated with the bus.
 17. An article of manufacturecomprising computer readable medium, wherein the computer readablemedium stores a plurality of executable instructions, and wherein theplurality of executable instructions cause: examining a scope associatedwith each of a plurality of timing violations; comparing the scopeassociated with each of the plurality of timing violations to a scopeassociated with each of a plurality of records in an array; updating oneof the records in the array, wherein a particular scope associated witha particular one of the plurality of the timing violations is the sameas the scope associated with said one of the records in the array; andadding a record to the array for a particular timing violation, whereinthe particular scope associated with the timing violation does not matchany of the scopes associated with any of the records in the array. 18.The article of manufacture of claim 17, wherein the plurality ofinstructions cause: determining whether the particular one of theplurality of timing violations is associated with a bus; and removing asuffix from the scope, wherein the particular one of the timingviolations is associated with the bus.